1. Field of the Invention
The present invention relates to a function cell, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell. More particularly, the present invention relates to a function cell used in cell-base semiconductor circuit designing, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell.
2. Description of the Background Art
The semiconductor circuit designing method of the cell-base type, represented by the standard cell type, is conventionally known as one of the semiconductor circuit designing methods. In the cell-base type semiconductor circuit designing method, circuit designing of semiconductor devices has been carried out by combining function cells, according to users"" demand, from a cell library that includes multiple kinds of function cells for realizing desired logic circuit functions.
FIGS. 11 and 12 are schematic plan views of function cells used in the conventional cell-base type semiconductor circuit designing method. FIG. 13 is an equivalent circuit diagram showing the logic circuit function realized by the function cells shown in FIGS. 11 and 12. Referring to FIGS. 11 to 13, the function cells will be described.
Referring first to FIG. 13, an inverter is realized in the function cells shown in FIGS. 11 and 12. The inverter circuit includes two transistors 120, 121. Transistors 120, 121 have their gate electrodes connected to an input terminal 112. Here, p type field effect transistor 120 has its source region connected to an interconnection for a power supply (hereinafter, referred to as a power-supply interconnection) 110 and its drain region connected to the drain region of n type field effect transistor 121 and to an output pin terminal 106a. Further, n type field effect transistor 121 has its source region connected to an interconnection for a ground (hereinafter, referred to as a ground interconnection) 111. The function cells shown in FIGS. 11 and 12 are formed to realize such a logic circuit.
Referring to FIG. 11, the function cell includes p type impurity diffusion regions 107a, 107b, n type impurity diffusion regions 107c, 107d, gate electrodes 108a, 108b, input pin terminal 112, output pin terminal 106a, power-supply interconnection 110, and ground interconnection 111. Impurity diffusion regions 107a to 107d are formed at a main surface of a semiconductor substrate. Between p type impurity diffusion regions 107a and 107b, gate electrode 108a is formed on the main surface of the semiconductor substrate with a gate insulation film (not shown) therebetween. Here, p type impurity diffusion regions 107a, 107b serving as source/drain regions, the gate insulation film, and gate electrode 108a constitute p type field effect transistor 120.
In another region of the function cell, n type impurity diffusion regions 107c, 107d, the gate insulation film, and gate electrode 108b also constitute n type field effect transistor 121. It is noted that n type field effect transistor 121 basically has a similar configuration to that of p type field effect transistor 120.
On impurity diffusion regions 107b, 107d, output pin terminal 106a is formed with an interlayer insulation film (not shown) therebetween. Output pin terminal 106a and impurity diffusion region 107b are electrically connected via contact holes 109g, 109h. Output pin terminal 106a and n type impurity diffusion region 107d are electrically connected via contact holes 109i, 109j. 
On p type impurity diffusion region 107a, power-supply interconnection 110 is formed with an interlayer insulation film (not shown) therebetween. Power-supply interconnection 110 and p type impurity diffusion region 107a are electrically connected via contact holes 109c, 109d. On n type impurity diffusion region 107c, ground interconnection 111 is formed with an interlayer insulation film (not shown) therebetween. Ground interconnection 111 and n type impurity diffusion region 107c are electrically connected via contact holes 109e, 109f. On gate electrodes 108a, 108b, input pin terminal 112 is formed with an interlayer insulation film (not shown) therebetween. Gate electrode 108a and input pin terminal 112 are electrically connected via contact hole 109a. Gate electrode 108b and input pin terminal 112 are electrically connected via contact hole 109b. 
A longitudinal pin access route to input pin terminal 112 (route of an external interconnection to input pin terminal 112) is denoted by 113a. Lateral pin access routes to input pin terminal 112 are denoted by 114a, 114b. A longitudinal pin access route to output pin terminal 106a is denoted by 113b. Lateral pin access routes to output pin terminal 106a are denoted by 115a to 115f. It is noted that the pin access route is a position in which a normally used route of an externally connected interconnection to input pin terminal 112, output pin terminal 106a or the like of the function cell can be set during circuit designing.
The longitudinal length (height) and lateral length (width) of the function cell are set at H7 and W7 so that they become as small as possible in accordance with the sizes of field effect transistors 120, 121 and the like.
FIG. 12 is a schematic plan view showing another function cell for realizing the logic circuit shown in FIG. 13, similarly to the function cell shown in FIG. 11. Referring to FIG. 12, the function cell basically has a similar configuration to that of the function cell shown in FIG. 11. In the function cell shown in FIG. 12, however, the size of impurity diffusion regions 107e to 107h is larger than that of impurity diffusion regions 107a to 107d. This is because, by changing the size of impurity diffusion regions 107e to 107h, the drivability of p type field effect transistor 120 and n type field effect transistor 121 is changed to realize electrical characteristics different from those of the function cell shown in FIG. 11.
Since the configuration of p type field effect transistor 120 and n type field effect transistor 121 is changed to change the electrical characteristics as described above, the external shape (longitudinal length H8 and lateral length W8, the external shape herein is determined by the longitudinal length and lateral length of a function cell) of the function cell shown in FIG. 12 becomes larger than the external shape (longitudinal length H7 and lateral length W7) of the function cell shown in FIG. 11.
Since the external shape of the function cell is changed in this manner, the size and position of input pin terminal 112 and output pin terminal 106b in the function cell shown in FIG. 12 are also changed as compared with the function cell shown in FIG. 11. Accordingly, the position of longitudinal pin access route 113c in the function cell shown in FIG. 12 is different from the position of longitudinal pin access route 113a in the function cell shown in FIG. 11. Similarly, the position of lateral pin access routes 114c, 114d in the function cell shown in FIG. 12 is also different from the position of lateral pin access routes 114a, 114b in the function cell shown in FIG. 11.
Further, the position of longitudinal pin access route 113d and lateral pin access routes 115g to 115n to output pin terminal 106b in the function cell shown in FIG. 12 is also different from the position of longitudinal pin access route 113b and lateral pin access routes 115a to 115f in the function cell shown in FIG. 11.
FIG. 14 is a flow chart of a conventional cell-base type semiconductor device circuit designing process using the function cells shown in FIGS. 11 and 12. Referring to FIG. 14, the flow of the conventional semiconductor circuit designing process will be described.
First, a step of selecting and placing function cells having a necessary function from a cell library (S1) is carried out. Then, a step of routing interconnections for connecting the placed function cells and connecting the function cells and an input/output circuit (S2) is carried out. Then, the verification test of circuit electrical characteristics (S3) is carried out as to whether a prescribed condition such as the condition of signal timing constraints is satisfied when the circuit formed of the function cells and the interconnections is supplied with a signal. When the prescribed condition is satisfied in the verification test (S3), circuit designing is ended (S6).
When the prescribed condition is not satisfied in the verification test (S3), however, a logic correction step (S4) is carried out. In the logic correction step (S4), the circuit is adjusted to satisfy the prescribed condition if a function cell that causes the dissatisfied condition is replaced by a function cell that has such electric characteristics, for example, of drivability and power consumption that satisfy the condition above even if the newly used function cell realizes the same logic circuit as the function cell to be replaced. Thereafter, as a result of the logic correction step (S4), a function cell replacement step (S5) of replacing the function cell to be changed with a function cell to be newly used is carried out.
Even if both of the function cells realize the same logic circuit, their gate widths are different if their electrical characteristics are different. Thus, the external shapes of the function cells are different as shown in FIGS. 11 and 12. As a result, when the function cells are simply replaced, the replaced function cell may overlap a neighboring function cell, or an unnecessary space may be created. Accordingly, a step of correcting the function cell placement (S7) has to be carried out. Since the function cell placement is corrected, there is a need to correct the routes for connecting the function cells and connecting the function cells and the input/output circuit. Thus, a step of correcting the routes of interconnections (S8) is carried out.
When the processing from the function cell replacement step (S5) to the routing (interconnection route) correction step (S8) is to be carried out, how the signal timing in the circuit, for example, is changed by the final cell placement and interconnection routes is estimated, and based on the estimate, the function cell replacement and the interconnection route correction are carried out to satisfy the condition of constraints. Since the estimate is not perfect, however, the verification test (S3) has to be carried out again after the interconnection route correction step (S8), as to whether the condition of constraints such as the condition of signal timing is satisfied.
According to the result of the verification test (S3), there is a case in which the logic correction step (S4), the function cell replacement step (S5), the function cell placement correction step (S7), the interconnection route correction step (S8) are repeated again, and the verification test (S3) for determining whether the condition of constraints is satisfied is also repeated. Accordingly, the time necessary to design semiconductor circuits is increased, which in turn increases the term for designing semiconductor devices. The increased term for designing has been a cause of the increased manufacturing cost of semiconductor devices.
One object of the present invention is to provide a function cell capable of shortening the term for designing semiconductor device circuits using the cell-base type semiconductor circuit designing method.
Another object of the present invention is to provide a semiconductor device capable of shortening the term for designing semiconductor device circuits even when the cell-base type semiconductor circuit designing method is used.
Still another object of the present invention is to provide a cell-base type semiconductor circuit designing method capable of shortening the term for designing semiconductor device circuits as compared with conventional methods.
A semiconductor device in one aspect of the present invention includes first and second function cells. The first and second function cells realize the same logic circuit function and have different electrical characteristics from each other. The first function cell includes a first externally connected interconnection. The second function cell includes a second externally connected interconnection. The external shape of the first function cell is almost the same as the external shape of the second function cell. The position of the first externally connected interconnection in the first function cell is almost the same as the position of the second externally connected interconnection in the second function cell.
It is assumed here that logic correction is carried so that the second function cell is used in stead of the first function cell to adjust signal timing, for example, when a semiconductor device circuit is designed in the semiconductor device manufacturing process. Since the external shapes of the first and second function cells are almost the same and the positions of the first and second externally connected interconnections in the first and second function cells are almost the same even in this case, the route of the externally connected interconnection (routing) that is determined on the premise that the first function cell is used can be applied as it is to the second function cell.
Since pin access routes in the first and second function cells can accordingly be made almost the same, the pin access routes do not have to be set again even when replacement of the first and second function cells is carried out. Since the external shapes of the first and second function cells are almost the same, the placement of the function cell does not have to be corrected. As a result, logic correction can be carried out easily by replacing the first and second function cells.
Even after logic correction is carried out, the placement of the function cell and the route of the externally connected interconnection are not changed. Accordingly, the condition of circuit constraints can reliably be satisfied by adjusting the electrical characteristics of the function cell. Thus, a verification test for determining whether the condition of constraints such as of signal timing does not have to be carried out again. As a result, the time necessary for the semiconductor device circuit designing process can substantially be reduced as compared with conventional processes.
Since a plurality of function cells that realize the same logic circuit function as the first function cell and have different electrical characteristics are prepared in a cell library used in semiconductor circuit designing, such a function cell having better electrical characteristics that realizes much higher speed and much lower power consumption of the semiconductor circuit can be selected from function cells that satisfy the condition of constraints such as of signal timing of the circuit. As a result, a semiconductor device capable of operating at high speed and a semiconductor device allowing low power consumption can be obtained more easily.
In the semiconductor device in the one aspect above, the first function cell may include a dummy interconnection formed almost on the same plane as the first externally connected interconnection. The position of a region occupied by the first externally connected interconnection and the dummy interconnection on the first function cell plane may be almost the same as the position of a region occupied by the second externally connected interconnection on the second function cell plane.
In this case, even when the outline of the first externally connected interconnection in the first function cell is different from the outline of the second externally connected interconnection in the second function cell, the position of the region occupied by the first externally connected interconnection and the dummy interconnection can be made almost the same as the position of the region occupied by the second externally connected interconnection by using the dummy interconnection. As a result, even when the positions of the first and second externally connected interconnections are determined automatically or semi-automatically such as by using an automatic routing program, the pin access route on the first function cell plane and the pin access route in the second function cell plane can be made almost the same more reliably.
Since the first and second function cells having different outlines of the first and second externally connected interconnections can be designed by using the dummy interconnection, the degree of freedom in designing the first and second function cells can be made higher.
In the semiconductor device in the one aspect above, the first function cell may include a first impurity diffusion region, and the second function cell may include a second impurity diffusion region. The impurity concentration in the first impurity diffusion region may be different from the impurity concentration in the second impurity diffusion region.
In this case, the electrical characteristics of the first and second function cells can be made different from each other by changing the impurity concentrations in the first and second impurity diffusion regions without changing the sizes of the first and second impurity diffusion regions and the configurations of electrodes and the like in the first and second function cells. As a result, the first and second function cells can be designed more easily.
Since the electrical characteristics of the first and second function cells are changed, the gate width, for example, of an field effect transistor in the function cell can not be adjusted, when it is to be adjusted, with accuracy higher than the accuracy of the minimum processed dimension in the photolithography process during semiconductor device formation. When the electrical characteristics are to be changed by adjusting the impurity concentration in the impurity diffusion region through controlling the amount of impurity implantation in the impurity diffusion region, the electrical characteristics can be adjusted more accurately than when they are changed by adjusting the gate width.
In the semiconductor device in the one aspect above, the first function cell may include a first element configuration including the first impurity diffusion region, and the second function cell may include a second element configuration including the second impurity diffusion region. The external shape of the first element configuration may be almost the same as the external shape of the second element configuration.
In this case, since the first and second element configurations in the first and second function cells can be made almost the same, the first and second function cells can be designed more easily. As a result, the effort necessary to produce the cell library that includes the first and second function cells can be reduced, and the manufacturing cost of the cell library can be lowered. Accordingly, the cost for developing and manufacturing semiconductor devices can be lowered.
In the semiconductor device in the one aspect above, the first function cell may include a first internal interconnection, and the second function cell may include a second internal interconnection. The material of the first internal interconnection may be different from the material of the second internal interconnection.
In this case, as a means of changing the electrical characteristics of the function cell, the electric resistance value, for example, of the internal interconnection can be adjusted by changing the material of the internal interconnection. As a result, the electrical characteristics of the function cell can be adjusted to a greater extent by changing the material of the internal interconnection as a means of adjusting the electrical characteristics of the first and second function cells.
In a semiconductor circuit designing method in another aspect of the present invention, a first function cell is selected and placed from a cell library that includes first and second function cells having different electrical characteristics from each other. A first pin access route in the first function cell is determined. The external shape of the first function cell is almost the same as the external shape of the second function cell. The first pin access route is almost the same as a second pin access route that is determined for the second function cell when the second function cell is selected and placed.
Accordingly, even when the first function cell is replaced by the second function cell to satisfy a condition of circuit constraints by adjusting signal timing, for example, in the semiconductor circuit, the function cell placement and the interconnection route for the function cell are not changed. Accordingly, the condition of circuit constraints can reliably be satisfied by adjusting the electrical characteristics of the function cell. Thus, the function cell placement and the interconnection route do not have to be corrected. As a result, it is not necessary to carry out again a verification test for determining whether the condition of constraints is satisfied and to repeat the processing from a logic correction step to an interconnection route correction step, differently from conventional methods. Thus, the time necessary to design semiconductor device circuits can be shortened.
In the semiconductor circuit designing method in the another aspect above, the steps of selecting and placing the second function cell, and determining the second pin access route in the second function cell may further be provided.
In the semiconductor circuit designing method in the another aspect above, the first function cell may include a first externally connected interconnection and a dummy interconnection. The dummy interconnection may be formed on the same plane as the first externally connected interconnection. The second function cell may include a second externally connected interconnection. The position of a region occupied by the first externally connected interconnection and the dummy interconnection on the first function cell plane may be almost the same as the position of a region occupied by the second externally connected interconnection on the second function cell plane.
In this case, even when the outline of the first externally connected interconnection in the first function cell is different from the outline of the second externally connected interconnection in the second function cell, the position of the region occupied by the first externally connected interconnection and the dummy interconnection can be made almost the same as the position of the region occupied by the second externally connected interconnection by using the dummy interconnection. As a result, even when the pin access routes to the first and second function cells are determined automatically or semi-automatically such as by using an automatic routing program, the pin access routes on the first and second function cell planes can be made almost the same more reliably.
Since the dummy interconnection is used, the first and second function cells having different outlines of the first and second externally connected interconnections can be designed. Thus, the degree of freedom in designing the first and second function cells can be made higher.
In the semiconductor circuit designing method in the another aspect above, the first function cell may include a first impurity diffusion region, and the second function cell may include a second impurity diffusion region. The impurity concentration in the first impurity diffusion region may be different from the impurity concentration in the second impurity diffusion region.
In this case, the electrical characteristics of the first and second function cells can be made different from each other by changing the impurity concentrations in the first and second impurity diffusion regions without changing the sizes of the first and second impurity diffusion regions and the configurations of electrodes and the like in the first and second function cells. As a result, the first and second function cells can be designed more easily.
Since the electrical characteristics of the first and second function cells are changed, the gate width, for example, of a field effect transistor in the function cell can not be changed, when it is to be changed, with accuracy higher than the accuracy of the minimum processed dimension in the photolithography process during semiconductor device formation. When the electrical characteristics are to be changed by adjusting the impurity concentration in the impurity diffusion region, the electrical characteristics can be changed more accurately than when they are adjusted by adjusting the gate width, for example, through controlling the amount of impurity implantation in the impurity diffusion region.
In the semiconductor circuit designing method in the another aspect above, the first function cell may include a first element configuration including the first impurity diffusion region, and the second function cell may include a second element configuration including the second impurity diffusion region. The external shape of the first element configuration may be almost the same as the external shape of the second element configuration.
In this case, since the first and second element configurations in the first and second function cells can be made almost the same, the first and second function cells can be designed more easily. As a result, the effort necessary to produce a cell library that includes the first and second function cells can be reduced, and the manufacturing cost of the cell library can be lowered. Accordingly, the cost for developing and manufacturing semiconductor devices can be lowered.
In the semiconductor circuit designing method in the another aspect above, the first function cell may include a first internal interconnection, and the second function cell may include a second internal interconnection. The material of the first internal interconnection may be different from the material of the second internal interconnection.
In this case, since the material of the internal interconnection can be changed as a means of changing the electrical characteristics of the function cell, the degree of freedom in designing the function cells of the cell library can be made higher.
A function cell in still another aspect of the present invention used in cell-base type semiconductor circuit designing includes first and second function cells that realize the same logic circuit function and have different electrical characteristics from each other. The first function cell includes a first externally connected interconnection. The second function cell includes a second externally connected interconnection. The external shape of the first function cell is almost the same as the external shape of the second function cell. The position of the first externally connected interconnection in the first function cell plane is almost the same as the position of the second externally connected interconnection on the second function cell plane.
It is assumed here that the first function cell is replaced by the second function cell having different electrical characteristics from those of the first function cell to satisfy a condition of circuit constraints such as of signal timing when the first function cell is used in semiconductor circuit designing. In this case, the first function cell only has to be replaced by the second function cell, and the function cell placement and the interconnection route do not have to be corrected. Accordingly, after logic correction is carried out to satisfy the condition of constraints, it is not necessary to carry out function cell replacement, function cell placement correction, interconnection route correction, and a verification retest to determine whether the condition of constraints is satisfied, differently from conventional methods. As a result, the time necessary to design semiconductor circuits can substantially be shortened as compared with conventional methods.
In the function cell in the still another aspect above, the first function cell may include a dummy interconnection formed on the same plane as the first externally connected interconnection. The position of a region occupied by the first externally connected interconnection and the dummy interconnection on the first function cell plane may be almost the same as the position of a region occupied by the second externally connected interconnection on the second function cell plane.
In this case, even when replacement of the first and second function cells is to be carried out, a pin access route of an interconnection for connecting an input/output pin terminal formed in the function cell to the outside can be made almost the same between the first and second function cells by making the position of the region occupied by the second externally connected interconnection almost the same as the position of the region occupied by the first externally connected interconnection and the dummy interconnection.
Since the dummy interconnection is formed, the pin access routes in the first and second function cells can be made almost the same even when the positions and the shapes of the first and second externally connected interconnections are different. As a result, the degree of freedom in designing the first and second interconnections can be made higher.
In the function cell in the still another aspect above, the first function cell may include a first impurity diffusion region, and the second function cell may include a second impurity diffusion region. The impurity concentration in the first impurity diffusion region may be different from the impurity concentration in the second impurity diffusion region.
In this case, the electrical characteristics of the first and second function cells can easily be adjusted differently by setting the first and second impurity diffusion regions to have different impurity concentrations.
When the shape of a component, such as the electrode width of a field effect transistor, which is a component of the function cell, is controlled in order to adjust the electrical characteristics of the first and second function cells, the accuracy of electrical characteristics adjustment is determined by the minimum processed dimension in the photolithography process for use in function cell formation. When the electrical characteristics such as electric resistance are to be adjusted by impurity concentration, however, the impurity concentration can be controlled by controlling the amount of impurity implantation, and the electrical characteristics of the function cell can be adjusted more accurately regardless of the minimum processed dimension.
In the function cell in the still another aspect above, the first function cell may include a first element configuration including the first impurity diffusion region, and the second function cell may include a second element configuration including the second impurity diffusion region. The external shape of the first element configuration may be almost the same as the external shape of the second element configuration.
In this case, since the first and second function cells have the same element configuration, the first and second function cells can be designed more easily. As a result, the cost for designing function cells can be reduced further.
In the function cell in the still another aspect above, the first function cell may include a first internal interconnection, and the second function cell may include a second internal interconnection. The material of the first internal interconnection may be different from the material of the second internal interconnection.
In this case, a means of changing the materials of the first and second internal interconnections can be used to adjust the electrical characteristics of the first and second function cells. Accordingly, the degree of freedom in designing the first and second function cells can be made higher.